High-Speed A/D Converter Core for 5G Base-Station Radio Receivers
| Reference number | |
| Coordinator | Lunds universitet - Institutionen för Elektro- och informationsteknik |
| Funding from Vinnova | SEK 3 525 000 |
| Project duration | September 2017 - August 2020 |
| Status | Completed |
| Venture | The strategic innovation programme Electronic Components and Systems: |
| Call | Electronic Components and System. Research and Innovation Projects 2017 |
Important results from the project
An asynchronous analog-to-digital data converter (ADC) using the so-called successive approximation (SAR) algorithm has been designed in a 22nm FD-SOI process by PhDl student Siyu Tan in close collaboration with Ericsson Research in Lund. Exhaustive simulations performed on the ADC (including layout parasitics) show that the sampling rate is higher than 400MHz and the resolution is close to 9 effective bits, which is very close to the targeted performance. An improved version of this ADC will form the basic block of the time-interleaved ADC to be developed in the next VINNOVA project.
Expected long term effects
PhD student Siyu Tan’s asynchronous SAR ADC, designed in a 22nm FD-SOI CMOS, will be tested as soon as the covid19 emergency at Ericsson in Lund allows. Nevertheless, simulations show that the expected performance will be very close to the project target. Siyu has also performed a more theoretical study of the performance difference between synchronous and asynchronous SAR ADCs, obtaining a better understanding of pros and cons for both. In particular, the robustness of the asynchronous ADC is superior when the sampling rate exceeds what the ADCs were designed for.
Approach and implementation
The asynchronous SAR ADC was designed from an existing synchronous SAR ADC developed at Ericsson Research in Lund. The main project objectives were to increase the ADC sampling rate and resolution, and to improve its robustness when the sampling rate exceeds the highest nominal rate. These objective have been achieved according to detailed simulations, although measurements are delayed due to the covid-19 emergency. This ADC is the basic block in a time-interleaved ADC intended for 5G / 6G radio communications, which will be developed in a follow-up VINNOVA project.